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Although ARM is marketed as RISC, it does have a lot of CISC-like features. I suspect the designers knew that with fixed-size instructions, they had to pack as much as they could into them to increase code density.


What would be CISC-like is if the opcode operated on memory locations, such that the CPU would have to deal with it taking a page fault.

Anyway, here's John Mashey, who helped design the MIPS, on RISC v CISC:

https://yarchive.net/comp/risc_definition.html




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